Patent · US Active

Apparatus and method for error correction and error detection

US9450613B2 · kind B2 · utility

4Cited by

7References

25Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Kern · Munich, DE
Ulrich Backhausen · Taufkirchen, DE
Thomas Rabenalt · Unterhaching, DE
Michael Goessel · Roter Dudel, DE
Klaus Oberlaender · San Jose, US
Christian Badack · Heinsberg, DE

Key dates

Filing date	Jul 10, 2014
Grant date	Sep 20, 2016
Priority date	—
Expiry date	Nov 21, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/6575
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.