Integrated circuit system having decoupled logical and physical interfaces
US9454484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Aug 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit system including a first integrated circuit chip including first logic, a second integrated circuit chip, and second logic distributed across the first and second integrated circuit chips. The second logic includes a first unit integrated in the first integrated circuit chip and a second unit integrated in the second integrated circuit chip. The integrated circuit system further includes a physical communication link coupling the first unit in the first integrated circuit chip and the second unit in the second integrated circuit chip and a request interface between the first logic and first unit of the second logic. The request interface is implemented in the first integrated circuit such that communication via the request interface between the first logic and the first unit of the second logic has low latency and such that the request interface is decoupled from the physical communication link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.