Semiconductor device
US9455016B2 · kind B2 · utility
2Cited by
1References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2013 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Feb 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40618
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.