Power management system for high traffic integrated circuit
US9455027B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Aug 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device can include a memory array section comprising a plurality of memory arrays that each include memory cells for storing data values; a data path section having switching circuits configured to enable data paths between the memory arrays and a plurality of input/outputs (I/Os) of the IC device; and a power fill control circuit configured to activate power-fill circuits in the IC device to perform non-mission mode operations that consume current, the amount of non-mission mode operations varying in response to mission mode circuit activity in the IC device; wherein mission mode circuit activity includes circuit activity resulting from a user input to the IC device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.