System architectures with data transfer paths between different memory types
US9455036B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2015 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Sep 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.