Semiconductor device and bump formation process
US9455183B2 · kind B2 · utility
7Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2013 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Apr 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.