Semiconductor package including multiple chips and separate groups of leads
US9455217B2 · kind B2 · utility
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12References
20Claims
0Family size
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Key dates
| Filing date | Oct 30, 2014 |
| Grant date | Sep 27, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.