Patent · US Active

System for preventing tampering with integrated circuit

US9455233B1 · kind B1 · utility

11Cited by

18References

17Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Rishi Bhooshan · Ghaziabad, IN
Mohit Arora · Faridabad, IN
Rakesh Pandey · Ghaziabad, IN

Key dates

Filing date	Dec 2, 2015
Grant date	Sep 27, 2016
Priority date	—
Expiry date	Dec 2, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/585
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes both a static wire mesh and an active wire mesh. The wire meshes can be formed in the same layer over the circuits to be protected or in different layers. The wire meshes also may cover the entire chip area or only predetermined areas, such as over secure memory and register areas. The wire meshes are connected to a tamper detection module, which monitors the meshes and any signals transmitted via the meshes to detect attempts to access the protected circuits via micro-probing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.