Decoupling capacitor using finFET topology

US9455251B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Todd A. Christensen · Rochester, US
• John E. Sheets, II · Zumbrota, US

Key dates

• Filing date: Jul 15, 2015
• Grant date: Sep 27, 2016
• Expiry date: Jul 15, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

Embodiments herein describe a decoupling capacitor that may include multiple fin and gate structures electrically insulated from a conductor (e.g., a metal layer) by a thin dielectric. The fins and gates may be electrically coupled to a first voltage rail (e.g., VHIGH) while the conductor is coupled to a second voltage rail (e.g., VLOW). In this manner, the fins and gates in combination form a first “plate” which is electrically insulated from the conductor which forms a second “plate” of a capacitor. In one embodiment, the decoupling capacitor is formed on the same substrate as the finFETs, and thus, can be disposed proximate to the finFETs—e.g., on the same layer in the chip or side-by-side. In one example, at least a portion of the decoupling capacitor and the finFET may be formed using the same fabrication steps.