John E. Sheets, II
24Patents
3h-index
16Co-inventors
56Inventor score
Filing activity: Jun 11, 2010 → Dec 3, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8300450B2 | Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variation | Electricity | 35 | Active |
| US9520876B1 | Power gating and clock gating in wiring levels | Electricity | 12 | Active |
| US8531203B2 | Mask alignment, rotation and bias monitor utilizing threshold voltage dependence | Electricity | 7 | Active |
| US9455251B1 | Decoupling capacitor using finFET topology | Electricity | 2 | Active |
| US10468491B1 | Low resistance contact for transistors | Electricity | 1 | Active |
| US10580730B2 | Managed integrated circuit power supply distribution | Physics | 1 | Active |
| US10332956B2 | Precision beol resistors | Electricity | 0 | Active |
| US11171063B2 | Metalization repair in semiconductor wafers | Electricity | 0 | Active |
| US10361265B2 | Precision BEOL resistors | Electricity | 0 | Active |
| US11018084B2 | Managed integrated circuit power supply distribution | Physics | 0 | Active |
| US10784159B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 0 | Active |
| US9570388B2 | FinFET power supply decoupling | Electricity | 0 | Active |
| US10943972B2 | Precision BEOL resistors | Electricity | 0 | Active |
| US9401643B1 | Bias-temperature induced damage mitigation circuit | Electricity | 0 | Active |
| US11171064B2 | Metalization repair in semiconductor wafers | Electricity | 0 | Active |
| US9966308B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 0 | Active |
| US9405311B1 | Bias-temperature induced damage mitigation circuit | Electricity | 0 | Active |
| US10256145B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 0 | Active |
| US10699950B2 | Method of optimizing wire RC for device performance and reliability | Electricity | 0 | Active |
| US9997408B2 | Method of optimizing wire RC for device performance and reliability | Electricity | 0 | Active |
| US10340330B2 | Precision BEOL resistors | Electricity | 0 | Active |
| US10332955B2 | Precision BEOL resistors | Electricity | 0 | Active |
| US10923575B2 | Low resistance contact for transistors | Electricity | 0 | Active |
| US12406119B2 | Processor chip timing adjustment enhancement | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.