Mixed mode integrated circuit, method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit
US9459317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3167
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit 100 comprises in addition to a clock network 110 an integrated test clock signal generator 140 to generate test clock signals that are provided via controllable multiplexers 150, 160 to an analog and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. The test clock signals are generated on basis of an input test clock signal having a controllable frequency. The clock network generates clock signals for the sub-circuitries that are used by the sub-circuitries under normal operational conditions. The controllable multiplexers provide either the test clock signal to a specific sub-circuitry or a clock signal received from the clock network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.