Semiconductor chip, stack chip including the same, and testing method thereof
US9459318B2 · kind B2 · utility
3Cited by
6References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Dec 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06596
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor chip includes an input pad and an output pad formed on the semiconductor chip; at least one bump formed on the semiconductor chip; and a test scan chain configured to output data applied from the input pad, to a node which is electrically coupled with the bump, store data corresponding to capacitance of the node by floating the node for a predetermined time, and output data corresponding to the stored capacitance, to the output pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.