Multi-level clock signal distribution network and integrated circuit
US9459651B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2011 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Nov 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.