Patent · US Active

Memory reference estimation method and device based on improved cache

US9460011B1 · kind B1 · utility

3Cited by

5References

19Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Marco Kraemer · Sindelfingen, DE
Carsten Otte · Stuttgart, DE
Christoph Raisch · Gerlingen, DE

Key dates

Filing date	Dec 14, 2015
Grant date	Oct 4, 2016
Priority date	—
Expiry date	Dec 14, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/621
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer system that includes a processor, a memory and a processor cache for the main memory with a check-in-cache instruction may be provided. The processor executes computer readable instructions stored in the memory that include receiving a check-in-cache instruction from a check-in-cache storage location. The instructions also include responsive to receiving the check-in-cache instruction, determining whether data bytes specified by the check-in-cache instruction are at least partially available in the processor cache. The instructions further include storing a condition code of the determination result in a storage location.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.