Methods of generating integrated circuit layout using standard cell library
US9460259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Aug 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.