Data-dependent self-biased differential sense amplifier
US9460760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2015 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jan 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.