Semiconductor devices having shielding pattern
US9461003B1 · kind B1 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jan 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/585
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a circuit pattern on a substrate, a shielding pattern on the circuit pattern and constituted by a plurality of parallel bars, and lower overlay marking on the shielding pattern and constituted by a plurality of parallel bars which define parallel slits between the bars. The pitch of the bars of the shielding pattern is smaller than the pitch of the bars of the lower overlay marking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.