Patent · US Active

System and method of varying gate lengths of multiple cores

US9461040B2 · kind B2 · utility

0Cited by

7References

30Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Ming Cai · Hopewell Junction, US
Samit Sengupta · San Jose, US
Chock Hing Gan · Singapore, SG
PR Chidambaram · Richardson, US

Key dates

Filing date	Jul 6, 2015
Grant date	Oct 4, 2016
Priority date	—
Expiry date	Jul 6, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.