Channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices
US9461168B1 · kind B1 · utility
7Cited by
1References
1Claims
0Family size
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Key dates
| Filing date | Feb 18, 2016 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Feb 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-gate finFET structure and formation thereof. The multi-gate finFET structure has a first gate structure that includes an inner side and an outer side. Adjacent to the first gate structure is a second gate structure. The inner side of the first gate structure faces, at least in part, the second gate structure. A stress-inducing material fills a fin cut trench that is adjacent to the outer side of the first gate structure. An epitaxial semiconductor layer fills, at least in part, an area between the first gate structure and the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.