Phase interpolator with phase traversing for delay-locked loop
US9461655B2 · kind B2 · utility
2Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2013 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jun 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system, method and computer readable storage medium are disclosed for phase interpolator to generate a single phase output clock signal based on plurality of phase-shifted component clock signals and a digital user input control signal to be utilized in combination with a delay-locked loop circuit. In one embodiment, the phase interpolator utilizes a method of phase-traversing when generating the single phase output clock signal that prevents over- or undershooting of the desired target phase of the single phase output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.