Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers
US9465740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Mar 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.