Sense amplifier layout for FinFET technology
US9466493B2 · kind B2 · utility
2Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2013 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.