Method for fabricating semiconductor structure
US9466522B2 · kind B2 · utility
3Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Mar 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor structure is provided. A substrate having a plurality of blocks is provided. Each of the blocks includes a first region and a second region. The first region and the second region are disposed alternately. A plurality of composite layers is formed on the substrate. The top-most layer of the composite layers is patterned. A plurality of composite blocks is formed on the first region of the substrate. The composite layers and the composite blocks on the blocks are removed successively by a removal process. A staircase structure is formed on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.