Apparatuses including stair-step structures and methods of forming the same
US9466531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Apr 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.