Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility
US9466534B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Dec 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
After forming transfer layer portions over a portion of a dielectric cap layer overlying a first portion of a substrate by a directed self-assembly process, a hard mask layer is formed over the dielectric cap layer to fill spaces between the transfer layer portions. Spacers are then formed over a portion of the hard mask layer overlying a second portion of the substrate by a sidewall image transfer process. A top semiconductor layer of the substrate is subsequently patterned using the transfer layer portions and the spacers as an etch mask to provide densely packed semiconductor fins in the first region and semi-isolated semiconductor fins in the second region of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.