Method of forming target patterns
US9466535B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Mar 3, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Mar 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming target patterns is disclosed. A substrate with multiple fins is provided. A plurality of mask patterns is formed across the fins and in at least a part of non-target areas. Target patterns are formed respectively in trenches between the mask patterns. The mask patterns are removed. With the disclosed method, the target patterns can be formed with substantially equal thickness. In the case that the target patterns are dummy gates, the conventional defects such as dummy gate residues or gate trench widening caused by uneven thicknesses are not observed upon the dummy gate removal step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.