Interconnect structure for an integrated circuit and method of fabricating an interconnect structure
US9466563B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 1, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Dec 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes first and second metallization levels. The first metallization level includes a first metal routing path. The second metallization level includes a dielectric layer having a via opening formed therein extending vertically through the dielectric layer to reach a top surface of the first metal routing path. A metal plug is deposited at a bottom of the via opening in direct contact with the first metal routing path. A remaining open area of the via opening is filled with a metal material to define a second metal routing path. The metal plug is formed of cobalt or an alloy including cobalt, and has an aspect ratio of greater than 0.3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.