Self-aligned contacts

US9466565B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mark Bohr · Beaverton, US
• Tahir Ghani · Portland, US
• Nadia M. Rahhai-Orabi · Hillsboro, US
• Subhash M. Joshi · Hillsboro, US
• Joseph M. Steigerwald · Forest Grove, US
• Jason W. Klaus · Portland, US
• Jack Hwang · Portland, US
• Ryan Mackiewicz · Beaverton, US

Key dates

• Filing date: Jun 4, 2015
• Grant date: Oct 11, 2016
• Expiry date: Jun 4, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/665
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.