Substrate comprising improved via pad placement in bump area
US9466578B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Apr 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.