Semiconductor structure having a dual-gate non-volatile memory device and methods for making same

US9466608B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Weize Chen · Phoenix, US
• Richard J. De Souza · Tempe, US
• Patrice M. Parris · Phoenix, US

Key dates

• Filing date: Oct 28, 2015
• Grant date: Oct 11, 2016
• Expiry date: Oct 28, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856

Abstract

A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.