3-dimensional nonvolatile memory device and method of manufacturing the same
US9466609B2 · kind B2 · utility
3Cited by
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12Claims
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Key dates
| Filing date | Nov 13, 2014 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Dec 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.