Patent · US Active

Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectrics

US9466661B2 · kind B2 · utility

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Key dates

Filing dateOct 10, 2014
Grant dateOct 11, 2016
Priority date
Expiry dateOct 10, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/212

Abstract

Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient α; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient α′ opposite in polarity but substantially equal in magnitude to α; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.