Planar mosfets and methods of fabrication, charge retention
US9466707B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 15, 2015 |
| Grant date | Oct 11, 2016 |
| Priority date | — |
| Expiry date | Feb 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A planar MOSFET includes a plurality of MOSFET cells. Each MOSFET cell includes an epitaxial layer of a first conductivity type, a body region of a second conductivity type inside the epitaxial layer, the second conductivity type having a polarity opposite to the first conductivity type, a source region inside the body region, a source contact portion to provide electrical contact with the source region, and a gate portion. A drift region is defined in the epitaxial layer between body regions of adjacent MOSFET cells and the gate portions of the adjacent MOSFET cells across said drift region are separated from each other with electrical insulation. A charge induction terminal is provided on the drift region to induce and store electric charge at said drift region upon application of a charge induction voltage at said charge induction terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.