Patent · US Active

Method and apparatus for controlling fetch-ahead in a VLES processor architecture

US9471321B2 · kind B2 · utility

1Cited by

2References

12Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Lev Vaskevich · Rehovot, IL
Mark Elnekave · Ramat Gan, IL
Yuval Peled · Kiryat Ono, IL
Idan Rozenberg · Nes Ziona, IL

Key dates

Filing date	Mar 30, 2011
Grant date	Oct 18, 2016
Priority date	—
Expiry date	Aug 28, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3853
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.