Technique for wafer-level processing of QFN packages
US9472451B2 · kind B2 · utility
0Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2014 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Oct 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.