Interconnect arrangement with stress-reducing structure and method of fabricating the same
US9472508B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 4, 2016 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jan 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.