Dummy metal structure and method of forming dummy metal structure
US9472509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2016 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | May 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.