Scannable flip-flop and low power scan-shift mode operation in a data processing system
US9473121B1 · kind B1 · utility
5Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2015 |
| Grant date | Oct 18, 2016 |
| Priority date | — |
| Expiry date | Jul 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A scannable flip-flop circuit and method for low power scan operation are provided. The scannable flip-flop includes a flip-flop for receiving an input signal, and for generating a flip-flop output signal. The scannable flip-flop also includes a voltage selection circuit coupled to the flip-flop. The voltage selection circuit supplies a first voltage to the flip-flop during a first state of a voltage selection signal, and supplies a second voltage to the flip-flop during a second state of the voltage selection signal. A series of scannable flip-flops may be arranged in a scan chain for testing during a scan test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.