Technologies for shadow stack manipulation for binary translation systems
US9477453B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jun 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native return address on to a native stack of the computing device, adds a constant offset to a stack pointer of the computing device, executes a native call instruction to a translated call target, and, after executing the native call instruction, subtracts the constant offset from the stack pointer. Executing the native call instruction pushes a translated return address onto a shadow stack of the computing device. The computing device may map two or more virtual memory pages of the shadow stack onto a single physical memory page. The computing device may execute a translated return routine that pops the native return address from the native stack, adds the constant offset to the stack pointer, and executes a native return instruction. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.