Instruction prefetch throttling using instruction count and branch prediction
US9477479B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Apr 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3869
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sequence of buffered instructions includes branch instructions. Branch prediction circuitry predicts if each branch instruction will result in a taken branch when executed. Normally, the fetch circuitry retrieves speculative instructions between the time that a source branch instruction is retrieved and the prediction if that source branch instruction will result in the taken branch. If the source branch instruction is predicted as taken, then the speculative instructions are discarded, and a count value indicates a number of instructions in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction predicted as taken, a throttled mode limits the number of instructions subsequently retrieved dependent on the count value, and then any further instructions are not retrieved for a number of clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.