System and method for partitioning of memory units into non-conflicting sets
US9477603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Apr 28, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.