Sahil Rihan
22Patents
9h-index
11Co-inventors
68Inventor score
Filing activity: Jun 30, 2003 → Feb 6, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7409487B1 | Virtualization system for computers that use address space indentifiers | Physics | 108 | Expired |
| US7478388B1 | Switching between multiple software entities using different operating modes of a processor in a computer system | Physics | 84 | Active |
| US8015388B1 | Bypassing guest page table walk for shadow page table entries not present in guest page table | Physics | 80 | Active |
| US7260815B1 | Method and apparatus for managing registers in a binary translator | Physics | 51 | Expired |
| US9304915B2 | Virtualization system using hardware assistance for page table coherence | Physics | 48 | Active |
| US8060722B2 | Hardware assistance for shadow page table coherence with guest page mappings | Physics | 14 | Active |
| US9164924B2 | Software cryptoprocessor | Physics | 11 | Active |
| US8443156B2 | Virtualization system using hardware assistance for shadow page table coherence | Physics | 10 | Active |
| US8838914B2 | Virtualization system using hardware assistance for shadow page table coherence | Physics | 9 | Active |
| US9477603B2 | System and method for partitioning of memory units into non-conflicting sets | Physics | 8 | Active |
| US9983894B2 | Method and system for providing secure system execution on hardware supporting secure application execution | Physics | 7 | Active |
| US9639482B2 | Software cryptoprocessor | Physics | 7 | Active |
| US10977367B1 | Detecting malicious firmware modification | Physics | 7 | Active |
| US9734092B2 | Secure support for I/O in software cryptoprocessor | Physics | 6 | Active |
| US9747450B2 | Attestation using a combined measurement and its constituent measurements | Physics | 4 | Active |
| US8762684B2 | Hardware assistance for page table coherence with guest page mappings | Physics | 3 | Active |
| US8266628B2 | Switching between multiple software entities using different operating modes of a processor | Physics | 3 | Active |
| US8219779B2 | Hardware assistance for shadow page table coherence with guest page mappings | Physics | 2 | Active |
| US8521504B1 | Method and apparatus for managing registers in a binary translator | Physics | 2 | Active |
| US10726131B2 | Systems and methods for mitigation of permanent denial of service attacks | Electricity | 1 | Active |
| US10037282B2 | System and method for partitioning of memory units into non-conflicting sets | Physics | 1 | Active |
| US10049048B1 | Method and system for using processor enclaves and cache partitioning to assist a software cryptoprocessor | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.