Memory having internal processors and data communication methods in memory
US9477636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2009 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.