Semiconductor memory device and operating method thereof
US9478261B1 · kind B1 · utility
6Cited by
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20Claims
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Key dates
| Filing date | Dec 9, 2015 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Dec 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device may include a memory cell array, a plurality of page buffers respectively connected to a plurality of bit lines of the memory cell array, and a control logic configured to control the plurality of page buffers to perform an operation on the memory cell array, wherein each of the plurality of page buffers senses a current amount, which varies according to a potential level of a corresponding bit line among the plurality of bit lines, at a sensing node to read data, and a precharge potential level at the sensing node is adjusted according to a temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.