Read-write contention circuitry

US9478278B1 · kind B1 · utility

Assignee

• Arm Limited · GB

Inventors

• Rejeesh Ammanath Vijayan · Bengaluru, IN
• Vikash · Bengaluru, IN
• Pradeep Raj · Atrauli, IN
• Neelima Gudipati · Bengaluru, IN
• Manish Trivedi · Ghaziabad, IN
• Sujit Kumar Rout · Bengaluru, IN

Key dates

• Filing date: Mar 31, 2015
• Grant date: Oct 25, 2016
• Expiry date: Mar 31, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/16
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.