Bit error rate mapping in a memory system
US9478315B2 · kind B2 · utility
8Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 3, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.