Memory device
US9478316B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2016 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jan 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a plurality of normal word lines; a plurality of redundancy word lines capable of replacing the word lines; a hammering information storage unit capable of storing an address of a row hammering word line of the normal word lines and the redundancy word lines; an address generation unit capable of generating an address of a normal word line or redundancy word line adjacent to a normal word line or redundancy word line corresponding to the address stored in the hammering information storage unit; and a refresh control unit capable of selecting the normal word line or redundancy word line corresponding to the address generated by the address generation unit for performing an additional refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.