Method for forming a superjunction device with improved ruggedness
US9478441B1 · kind B1 · utility
7Cited by
36References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2010 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Aug 3, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.