Method for manufacturing through-hole silicon via
US9478464B2 · kind B2 · utility
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Key dates
| Filing date | Apr 30, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Apr 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68359
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.