Vertical gate transistor and pixel structure comprising such a transistor
US9478570B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 30, 2015 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Oct 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/813
Abstract
The present disclosure relates to a photodiode comprising: a P-conductivity type substrate region, an electric charge collecting region for collecting electric charges appearing when a rear face of the substrate region receives light, the collecting region comprising an N-conductivity type region formed deep in the substrate region, an N-conductivity type read region formed in the substrate region, and an isolated transfer gate, formed in the substrate region in a deep isolating trench extending opposite a lateral face of the N-conductivity type region, next to the read region, and arranged for receiving a gate voltage to transfer electric charges stored in the collecting region toward the read region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.